In many signal processing systems a plurality of input signals are received and some or all of these signals are processed to form one or more output signals. The output signals are provided to one or more output devices for further processing or reproduction. In systems where digital domain processing is required it is common to receive the digital signal and/or an analog input signal (which is then converted to a digital signal), pre-process and route and process the digitized signals. As technology advances, data signals contain an increasing amount of information and increasing numbers of signals are processed to form output signals. For example, television signals have increasingly higher resolutions and multiple of signals are often combined on a single display.
As the number and complexity of the input signals increases it can become increasing difficult to successfully route the digitized versions of the input signals to appropriate signal processors. For example, in one existing system, a plurality of input signals are received and are potentially initially digitized and packetized to provide a plurality of packetized signal streams each of which corresponds to a number of the input signals. The packetized streams are provided to a packet router, typically on a common transmission line. The packet router is configured to route a subset of signals to each of a number of output devices. Each output device then process each of the packetized signals that it receives to produce an output signal.
Such systems have bottlenecks associated with the initial pre-processing process in terms of processor speeds, overall memory bandwidth requirements, memory controller speeds, memory sizes and memory interfaces. In addition, such systems have bottlenecks associated with the transmission capacity of the transmission lines carrying the packetized input signals, which may be time division multiplexed communication lines. There are also bottlenecks in the packet router associated with processor speeds, overall memory bandwidth requirements, memory controller speeds, memory sizes and memory interfaces. There are bottlenecks associated with the data capacities of the communication links between the packet router and the output cards which may also be time division multiplexed or otherwise shared communication links. Finally, the output cards have similar bottlenecks as the input cards and the packet processors in terms of processor speeds, overall memory bandwidth requirements, memory controller speeds, memory sizes and memory interfaces.
There is a need for a simple and low cost system that alleviates these system bottlenecks and allows for a plurality of input signals to be selected and routed to one or more output processors each of which processes the input signals selected in relation to that output processor and each of which provides one or more output signals based on the input signals coupled to it.